Indirect:
00[address] ax <- ax and mem[mem[address]]
01[address] bx <- bx and mem[mem[address]]
02[address] cx <- cx and mem[mem[address]]
03[address] dx <- dx and mem[mem[address]]
04[address] ex <- ex and mem[mem[address]]
Direct:
05[address] ax <- ax and mem[address]
06[address] bx <- bx and mem[address]
07[address] cx <- cx and mem[address]
08[address] dx <- dx and mem[address]
09[address] ex <- ex and mem[address]
Immediate:
0a[number] ax <- ax and number
0b[number] bx <- bx and number
0c[number] cx <- cx and number
0d[number] dx <- dx and number
0e[number] ex <- ex and number
Register memory addressing:
0f0000 ax <- ax and mem[ax]
0f0001 ax <- ax and mem[bx]
0f0002 ax <- ax and mem[cx]
0f0003 ax <- ax and mem[dx]
0f0004 ax <- ax and mem[ex]
0f0005 bx <- bx and mem[ax]
0f0006 bx <- bx and mem[bx]
0f0007 bx <- bx and mem[cx]
0f0008 bx <- bx and mem[dx]
0f0009 bx <- bx and mem[ex]
0f000a cx <- cx and mem[ax]
0f000b cx <- cx and mem[bx]
0f000c cx <- cx and mem[cx]
0f000d cx <- cx and mem[dx]
0f000e cx <- cx and mem[ex]
0f000f dx <- dx and mem[ax]
0f0010 dx <- dx and mem[bx]
0f0011 dx <- dx and mem[cx]
0f0012 dx <- dx and mem[dx]
0f0013 dx <- dx and mem[ex]
0f0014 ex <- ex and mem[ax]
0f0015 ex <- ex and mem[bx]
0f0016 ex <- ex and mem[cx]
0f0017 ex <- ex and mem[dx]
0f0018 ex <- ex and mem[ex]
Register addressing:
100000 ax <- ax and ax
100001 ax <- ax and bx
100002 ax <- ax and cx
100003 ax <- ax and dx
100004 ax <- ax and ex
100005 bx <- bx and ax
100006 bx <- bx and bx
100007 bx <- bx and cx
100008 bx <- bx and dx
100009 bx <- bx and ex
10000a cx <- cx and ax
10000b cx <- cx and bx
10000c cx <- cx and cx
10000d cx <- cx and dx
10000e cx <- cx and ex
10000f dx <- dx and ax
100010 dx <- dx and bx
100011 dx <- dx and cx
100012 dx <- dx and dx
100013 dx <- dx and ex
100014 ex <- ex and ax
100015 ex <- ex and bx
100016 ex <- ex and cx
100017 ex <- ex and dx
100018 ex <- ex and ex

Indirect:
11[address] ax <- ax or mem[mem[address]]
12[address] bx <- bx or mem[mem[address]]
13[address] cx <- cx or mem[mem[address]]
14[address] dx <- dx or mem[mem[address]]
15[address] ex <- ex or mem[mem[address]]
Direct:
16[address] ax <- ax or mem[address]
17[address] bx <- bx or mem[address]
18[address] cx <- cx or mem[address]
19[address] dx <- dx or mem[address]
1a[address] ex <- ex or mem[address]
Immediate:
1b[number] ax <- ax or number
1c[number] bx <- bx or number
1d[number] cx <- cx or number
1e[number] dx <- dx or number
1f[number] ex <- ex or number
Register memory addressing:
200000 ax <- ax or mem[ax]
200001 ax <- ax or mem[bx]
200002 ax <- ax or mem[cx]
200003 ax <- ax or mem[dx]
200004 ax <- ax or mem[ex]
200005 bx <- bx or mem[ax]
200006 bx <- bx or mem[bx]
200007 bx <- bx or mem[cx]
200008 bx <- bx or mem[dx]
200009 bx <- bx or mem[ex]
20000a cx <- cx or mem[ax]
20000b cx <- cx or mem[bx]
20000c cx <- cx or mem[cx]
20000d cx <- cx or mem[dx]
20000e cx <- cx or mem[ex]
20000f dx <- dx or mem[ax]
200010 dx <- dx or mem[bx]
200011 dx <- dx or mem[cx]
200012 dx <- dx or mem[dx]
200013 dx <- dx or mem[ex]
200014 ex <- ex or mem[ax]
200015 ex <- ex or mem[bx]
200016 ex <- ex or mem[cx]
200017 ex <- ex or mem[dx]
200018 ex <- ex or mem[ex]
Register addressing:
210000 ax <- ax or ax
210001 ax <- ax or bx
210002 ax <- ax or cx
210003 ax <- ax or dx
210004 ax <- ax or ex
210005 bx <- bx or ax
210006 bx <- bx or bx
210007 bx <- bx or cx
210008 bx <- bx or dx
210009 bx <- bx or ex
21000a cx <- cx or ax
21000b cx <- cx or bx
21000c cx <- cx or cx
21000d cx <- cx or dx
21000e cx <- cx or ex
21000f dx <- dx or ax
210010 dx <- dx or bx
210011 dx <- dx or cx
210012 dx <- dx or dx
210013 dx <- dx or ex
210014 ex <- ex or ax
210015 ex <- ex or bx
210016 ex <- ex or cx
210017 ex <- ex or dx
210018 ex <- ex or ex

Indirect:
22[address] ax <- ax xor mem[mem[address]]
23[address] bx <- bx xor mem[mem[address]]
24[address] cx <- cx xor mem[mem[address]]
25[address] dx <- dx xor mem[mem[address]]
26[address] ex <- ex xor mem[mem[address]]
Direct:
27[address] ax <- ax xor mem[address]
28[address] bx <- bx xor mem[address]
29[address] cx <- cx xor mem[address]
2a[address] dx <- dx xor mem[address]
2b[address] ex <- ex xor mem[address]
Immediate:
2c[number] ax <- ax xor number
2d[number] bx <- bx xor number
2e[number] cx <- cx xor number
2f[number] dx <- dx xor number
30[number] ex <- ex xor number
Register memory addressing:
310000 ax <- ax xor mem[ax]
310001 ax <- ax xor mem[bx]
310002 ax <- ax xor mem[cx]
310003 ax <- ax xor mem[dx]
310004 ax <- ax xor mem[ex]
310005 bx <- bx xor mem[ax]
310006 bx <- bx xor mem[bx]
310007 bx <- bx xor mem[cx]
310008 bx <- bx xor mem[dx]
310009 bx <- bx xor mem[ex]
31000a cx <- cx xor mem[ax]
31000b cx <- cx xor mem[bx]
31000c cx <- cx xor mem[cx]
31000d cx <- cx xor mem[dx]
31000e cx <- cx xor mem[ex]
31000f dx <- dx xor mem[ax]
310010 dx <- dx xor mem[bx]
310011 dx <- dx xor mem[cx]
310012 dx <- dx xor mem[dx]
310013 dx <- dx xor mem[ex]
310014 ex <- ex xor mem[ax]
310015 ex <- ex xor mem[bx]
310016 ex <- ex xor mem[cx]
310017 ex <- ex xor mem[dx]
310018 ex <- ex xor mem[ex]
Register addressing:
320000 ax <- ax xor ax
320001 ax <- ax xor bx
320002 ax <- ax xor cx
320003 ax <- ax xor dx
320004 ax <- ax xor ex
320005 bx <- bx xor ax
320006 bx <- bx xor bx
320007 bx <- bx xor cx
320008 bx <- bx xor dx
320009 bx <- bx xor ex
32000a cx <- cx xor ax
32000b cx <- cx xor bx
32000c cx <- cx xor cx
32000d cx <- cx xor dx
32000e cx <- cx xor ex
32000f dx <- dx xor ax
320010 dx <- dx xor bx
320011 dx <- dx xor cx
320012 dx <- dx xor dx
320013 dx <- dx xor ex
320014 ex <- ex xor ax
320015 ex <- ex xor bx
320016 ex <- ex xor cx
320017 ex <- ex xor dx
320018 ex <- ex xor ex

Indirect:
33[address] ax <- ax + mem[mem[address]]
34[address] bx <- bx + mem[mem[address]]
35[address] cx <- cx + mem[mem[address]]
36[address] dx <- dx + mem[mem[address]]
37[address] ex <- ex + mem[mem[address]]
Direct:
38[address] ax <- ax + mem[address]
39[address] bx <- bx + mem[address]
3a[address] cx <- cx + mem[address]
3b[address] dx <- dx + mem[address]
3c[address] ex <- ex + mem[address]
Immediate:
3d[number] ax <- ax + number
3e[number] bx <- bx + number
3f[number] cx <- cx + number
40[number] dx <- dx + number
41[number] ex <- ex + number
Register memory addressing:
420000 ax <- ax + mem[ax]
420001 ax <- ax + mem[bx]
420002 ax <- ax + mem[cx]
420003 ax <- ax + mem[dx]
420004 ax <- ax + mem[ex]
420005 bx <- bx + mem[ax]
420006 bx <- bx + mem[bx]
420007 bx <- bx + mem[cx]
420008 bx <- bx + mem[dx]
420009 bx <- bx + mem[ex]
42000a cx <- cx + mem[ax]
42000b cx <- cx + mem[bx]
42000c cx <- cx + mem[cx]
42000d cx <- cx + mem[dx]
42000e cx <- cx + mem[ex]
42000f dx <- dx + mem[ax]
420010 dx <- dx + mem[bx]
420011 dx <- dx + mem[cx]
420012 dx <- dx + mem[dx]
420013 dx <- dx + mem[ex]
420014 ex <- ex + mem[ax]
420015 ex <- ex + mem[bx]
420016 ex <- ex + mem[cx]
420017 ex <- ex + mem[dx]
420018 ex <- ex + mem[ex]
Register addressing:
430000 ax <- ax + ax
430001 ax <- ax + bx
430002 ax <- ax + cx
430003 ax <- ax + dx
430004 ax <- ax + ex
430005 bx <- bx + ax
430006 bx <- bx + bx
430007 bx <- bx + cx
430008 bx <- bx + dx
430009 bx <- bx + ex
43000a cx <- cx + ax
43000b cx <- cx + bx
43000c cx <- cx + cx
43000d cx <- cx + dx
43000e cx <- cx + ex
43000f dx <- dx + ax
430010 dx <- dx + bx
430011 dx <- dx + cx
430012 dx <- dx + dx
430013 dx <- dx + ex
430014 ex <- ex + ax
430015 ex <- ex + bx
430016 ex <- ex + cx
430017 ex <- ex + dx
430018 ex <- ex + ex

Indirect:
44[address] ax <- ax + mem[mem[address]] + C
45[address] bx <- bx + mem[mem[address]] + C
46[address] cx <- cx + mem[mem[address]] + C
47[address] dx <- dx + mem[mem[address]] + C
48[address] ex <- ex + mem[mem[address]] + C
Direct:
49[address] ax <- ax + mem[address] + C
4a[address] bx <- bx + mem[address] + C
4b[address] cx <- cx + mem[address] + C
4c[address] dx <- dx + mem[address] + C
4d[address] ex <- ex + mem[address] + C
Immediate:
4e[number] ax <- ax + number + C
4f[number] bx <- bx + number + C
50[number] cx <- cx + number + C
51[number] dx <- dx + number + C
52[number] ex <- ex + number + C
Register memory addressing:
530000 ax <- ax + mem[ax] + C
530001 ax <- ax + mem[bx] + C
530002 ax <- ax + mem[cx] + C
530003 ax <- ax + mem[dx] + C
530004 ax <- ax + mem[ex] + C
530005 bx <- bx + mem[ax] + C
530006 bx <- bx + mem[bx] + C
530007 bx <- bx + mem[cx] + C
530008 bx <- bx + mem[dx] + C
530009 bx <- bx + mem[ex] + C
53000a cx <- cx + mem[ax] + C
53000b cx <- cx + mem[bx] + C
53000c cx <- cx + mem[cx] + C
53000d cx <- cx + mem[dx] + C
53000e cx <- cx + mem[ex] + C
53000f dx <- dx + mem[ax] + C
530010 dx <- dx + mem[bx] + C
530011 dx <- dx + mem[cx] + C
530012 dx <- dx + mem[dx] + C
530013 dx <- dx + mem[ex] + C
530014 ex <- ex + mem[ax] + C
530015 ex <- ex + mem[bx] + C
530016 ex <- ex + mem[cx] + C
530017 ex <- ex + mem[dx] + C
530018 ex <- ex + mem[ex] + C
Register addressing:
540000 ax <- ax + ax + C
540001 ax <- ax + bx + C
540002 ax <- ax + cx + C
540003 ax <- ax + dx + C
540004 ax <- ax + ex + C
540005 bx <- bx + ax + C
540006 bx <- bx + bx + C
540007 bx <- bx + cx + C
540008 bx <- bx + dx + C
540009 bx <- bx + ex + C
54000a cx <- cx + ax + C
54000b cx <- cx + bx + C
54000c cx <- cx + cx + C
54000d cx <- cx + dx + C
54000e cx <- cx + ex + C
54000f dx <- dx + ax + C
540010 dx <- dx + bx + C
540011 dx <- dx + cx + C
540012 dx <- dx + dx + C
540013 dx <- dx + ex + C
540014 ex <- ex + ax + C
540015 ex <- ex + bx + C
540016 ex <- ex + cx + C
540017 ex <- ex + dx + C
540018 ex <- ex + ex + C

Indirect:
55[address] ax <- ax - mem[mem[address]]
56[address] bx <- bx - mem[mem[address]]
57[address] cx <- cx - mem[mem[address]]
58[address] dx <- dx - mem[mem[address]]
59[address] ex <- ex - mem[mem[address]]
Direct:
5a[address] ax <- ax - mem[address]
5b[address] bx <- bx - mem[address]
5c[address] cx <- cx - mem[address]
5d[address] dx <- dx - mem[address]
5e[address] ex <- ex - mem[address]
Immediate:
5f[number] ax <- ax - number
60[number] bx <- bx - number
61[number] cx <- cx - number
62[number] dx <- dx - number
63[number] ex <- ex - number
Register memory addressing:
640000 ax <- ax - mem[ax]
640001 ax <- ax - mem[bx]
640002 ax <- ax - mem[cx]
640003 ax <- ax - mem[dx]
640004 ax <- ax - mem[ex]
640005 bx <- bx - mem[ax]
640006 bx <- bx - mem[bx]
640007 bx <- bx - mem[cx]
640008 bx <- bx - mem[dx]
640009 bx <- bx - mem[ex]
64000a cx <- cx - mem[ax]
64000b cx <- cx - mem[bx]
64000c cx <- cx - mem[cx]
64000d cx <- cx - mem[dx]
64000e cx <- cx - mem[ex]
64000f dx <- dx - mem[ax]
640010 dx <- dx - mem[bx]
640011 dx <- dx - mem[cx]
640012 dx <- dx - mem[dx]
640013 dx <- dx - mem[ex]
640014 ex <- ex - mem[ax]
640015 ex <- ex - mem[bx]
640016 ex <- ex - mem[cx]
640017 ex <- ex - mem[dx]
640018 ex <- ex - mem[ex]
Register addressing:
650000 ax <- ax - ax
650001 ax <- ax - bx
650002 ax <- ax - cx
650003 ax <- ax - dx
650004 ax <- ax - ex
650005 bx <- bx - ax
650006 bx <- bx - bx
650007 bx <- bx - cx
650008 bx <- bx - dx
650009 bx <- bx - ex
65000a cx <- cx - ax
65000b cx <- cx - bx
65000c cx <- cx - cx
65000d cx <- cx - dx
65000e cx <- cx - ex
65000f dx <- dx - ax
650010 dx <- dx - bx
650011 dx <- dx - cx
650012 dx <- dx - dx
650013 dx <- dx - ex
650014 ex <- ex - ax
650015 ex <- ex - bx
650016 ex <- ex - cx
650017 ex <- ex - dx
650018 ex <- ex - ex

Indirect:
66[address] ax <- ax - mem[mem[address]] - C
67[address] bx <- bx - mem[mem[address]] - C
68[address] cx <- cx - mem[mem[address]] - C
69[address] dx <- dx - mem[mem[address]] - C
6a[address] ex <- ex - mem[mem[address]] - C
Direct:
6b[address] ax <- ax - mem[address] - C
6c[address] bx <- bx - mem[address] - C
6d[address] cx <- cx - mem[address] - C
6e[address] dx <- dx - mem[address] - C
6f[address] ex <- ex - mem[address] - C
Immediate:
70[number] ax <- ax - number - C
71[number] bx <- bx - number - C
72[number] cx <- cx - number - C
73[number] dx <- dx - number - C
74[number] ex <- ex - number - C
Register memory addressing:
750000 ax <- ax - mem[ax] - C
750001 ax <- ax - mem[bx] - C
750002 ax <- ax - mem[cx] - C
750003 ax <- ax - mem[dx] - C
750004 ax <- ax - mem[ex] - C
750005 bx <- bx - mem[ax] - C
750006 bx <- bx - mem[bx] - C
750007 bx <- bx - mem[cx] - C
750008 bx <- bx - mem[dx] - C
750009 bx <- bx - mem[ex] - C
75000a cx <- cx - mem[ax] - C
75000b cx <- cx - mem[bx] - C
75000c cx <- cx - mem[cx] - C
75000d cx <- cx - mem[dx] - C
75000e cx <- cx - mem[ex] - C
75000f dx <- dx - mem[ax] - C
750010 dx <- dx - mem[bx] - C
750011 dx <- dx - mem[cx] - C
750012 dx <- dx - mem[dx] - C
750013 dx <- dx - mem[ex] - C
750014 ex <- ex - mem[ax] - C
750015 ex <- ex - mem[bx] - C
750016 ex <- ex - mem[cx] - C
750017 ex <- ex - mem[dx] - C
750018 ex <- ex - mem[ex] - C
Register addressing:
760000 ax <- ax - ax - C
760001 ax <- ax - bx - C
760002 ax <- ax - cx - C
760003 ax <- ax - dx - C
760004 ax <- ax - ex - C
760005 bx <- bx - ax - C
760006 bx <- bx - bx - C
760007 bx <- bx - cx - C
760008 bx <- bx - dx - C
760009 bx <- bx - ex - C
76000a cx <- cx - ax - C
76000b cx <- cx - bx - C
76000c cx <- cx - cx - C
76000d cx <- cx - dx - C
76000e cx <- cx - ex - C
76000f dx <- dx - ax - C
760010 dx <- dx - bx - C
760011 dx <- dx - cx - C
760012 dx <- dx - dx - C
760013 dx <- dx - ex - C
760014 ex <- ex - ax - C
760015 ex <- ex - bx - C
760016 ex <- ex - cx - C
760017 ex <- ex - dx - C
760018 ex <- ex - ex - C

Indirect:
77[address] ax <- (ax x mem[mem[address]])(0-15), bx <- (ax x mem[mem[address]])(16-31)
78[address] bx <- (bx x mem[mem[address]])(0-15), cx <- (bx x mem[mem[address]])(16-31)
79[address] cx <- (cx x mem[mem[address]])(0-15), dx <- (cx x mem[mem[address]])(16-31)
7a[address] dx <- (dx x mem[mem[address]])(0-15), ex <- (dx x mem[mem[address]])(16-31)
7b[address] ex <- (ex x mem[mem[address]])(0-15), ax <- (ex x mem[mem[address]])(16-31)
Direct:
7c[address] ax <- (ax x mem[address])(0-15), bx <- (ax x mem[address])(16-31)
7d[address] bx <- (bx x mem[address])(0-15), cx <- (bx x mem[address])(16-31)
7e[address] cx <- (cx x mem[address])(0-15), dx <- (cx x mem[address])(16-31)
7f[address] dx <- (dx x mem[address])(0-15), ex <- (dx x mem[address])(16-31)
80[address] ex <- (ex x mem[address])(0-15), ax <- (ex x mem[address])(16-31)
Immediate:
81[number] ax <- (ax x number)(0-15), bx <- (ax x number)(16-31)
82[number] bx <- (bx x number)(0-15), cx <- (bx x number)(16-31)
83[number] cx <- (cx x number)(0-15), dx <- (cx x number)(16-31)
84[number] dx <- (dx x number)(0-15), ex <- (dx x number)(16-31)
85[number] ex <- (ex x number)(0-15), ax <- (ex x number)(16-31)
Register memory addressing:
860000 ax <- (ax x mem[ax])(0-15), bx <- (ax x mem[ax])(16-31)
860001 ax <- (ax x mem[bx])(0-15), bx <- (ax x mem[bx])(16-31)
860002 ax <- (ax x mem[cx])(0-15), bx <- (ax x mem[cx])(16-31)
860003 ax <- (ax x mem[dx])(0-15), bx <- (ax x mem[dx])(16-31)
860004 ax <- (ax x mem[ex])(0-15), bx <- (ax x mem[ex])(16-31)
860005 bx <- (bx x mem[ax])(0-15), cx <- (bx x mem[ax])(16-31)
860006 bx <- (bx x mem[bx])(0-15), cx <- (bx x mem[bx])(16-31)
860007 bx <- (bx x mem[cx])(0-15), cx <- (bx x mem[cx])(16-31)
860008 bx <- (bx x mem[dx])(0-15), cx <- (bx x mem[dx])(16-31)
860009 bx <- (bx x mem[ex])(0-15), cx <- (bx x mem[ex])(16-31)
86000a cx <- (cx x mem[ax])(0-15), dx <- (cx x mem[ax])(16-31)
86000b cx <- (cx x mem[bx])(0-15), dx <- (cx x mem[bx])(16-31)
86000c cx <- (cx x mem[cx])(0-15), dx <- (cx x mem[cx])(16-31)
86000d cx <- (cx x mem[dx])(0-15), dx <- (cx x mem[dx])(16-31)
86000e cx <- (cx x mem[ex])(0-15), dx <- (cx x mem[ex])(16-31)
86000f dx <- (dx x mem[ax])(0-15), ex <- (dx x mem[ax])(16-31)
860010 dx <- (dx x mem[bx])(0-15), ex <- (dx x mem[bx])(16-31)
860011 dx <- (dx x mem[cx])(0-15), ex <- (dx x mem[cx])(16-31)
860012 dx <- (dx x mem[dx])(0-15), ex <- (dx x mem[dx])(16-31)
860013 dx <- (dx x mem[ex])(0-15), ex <- (dx x mem[ex])(16-31)
860014 ex <- (ex x mem[ax])(0-15), ax <- (ex x mem[ax])(16-31)
860015 ex <- (ex x mem[bx])(0-15), ax <- (ex x mem[bx])(16-31)
860016 ex <- (ex x mem[cx])(0-15), ax <- (ex x mem[cx])(16-31)
860017 ex <- (ex x mem[dx])(0-15), ax <- (ex x mem[dx])(16-31)
860018 ex <- (ex x mem[ex])(0-15), ax <- (ex x mem[ex])(16-31)
Register addressing:
870000 ax <- (ax x ax)(0-15), bx <- (ax x ax)(16-31)
870001 ax <- (ax x bx)(0-15), bx <- (ax x bx)(16-31)
870002 ax <- (ax x cx)(0-15), bx <- (ax x cx)(16-31)
870003 ax <- (ax x dx)(0-15), bx <- (ax x dx)(16-31)
870004 ax <- (ax x ex)(0-15), bx <- (ax x ex)(16-31)
870005 bx <- (bx x ax)(0-15), cx <- (bx x ax)(16-31)
870006 bx <- (bx x bx)(0-15), cx <- (bx x bx)(16-31)
870007 bx <- (bx x cx)(0-15), cx <- (bx x cx)(16-31)
870008 bx <- (bx x dx)(0-15), cx <- (bx x dx)(16-31)
870009 bx <- (bx x ex)(0-15), cx <- (bx x ex)(16-31)
87000a cx <- (cx x ax)(0-15), dx <- (cx x ax)(16-31)
87000b cx <- (cx x bx)(0-15), dx <- (cx x bx)(16-31)
87000c cx <- (cx x cx)(0-15), dx <- (cx x cx)(16-31)
87000d cx <- (cx x dx)(0-15), dx <- (cx x dx)(16-31)
87000e cx <- (cx x ex)(0-15), dx <- (cx x ex)(16-31)
87000f dx <- (dx x ax)(0-15), ex <- (dx x ax)(16-31)
870010 dx <- (dx x bx)(0-15), ex <- (dx x bx)(16-31)
870011 dx <- (dx x cx)(0-15), ex <- (dx x cx)(16-31)
870012 dx <- (dx x dx)(0-15), ex <- (dx x dx)(16-31)
870013 dx <- (dx x ex)(0-15), ex <- (dx x ex)(16-31)
870014 ex <- (ex x ax)(0-15), ax <- (ex x ax)(16-31)
870015 ex <- (ex x bx)(0-15), ax <- (ex x bx)(16-31)
870016 ex <- (ex x cx)(0-15), ax <- (ex x cx)(16-31)
870017 ex <- (ex x dx)(0-15), ax <- (ex x dx)(16-31)
870018 ex <- (ex x ex)(0-15), ax <- (ex x ex)(16-31)

Indirect:
88[address] ax <- ax / mem[mem[address]], bx <- ax % mem[mem[address]]
89[address] bx <- bx / mem[mem[address]], cx <- bx % mem[mem[address]]
8a[address] cx <- cx / mem[mem[address]], dx <- cx % mem[mem[address]]
8b[address] dx <- dx / mem[mem[address]], ex <- dx % mem[mem[address]]
8c[address] ex <- ex / mem[mem[address]], ax <- ex % mem[mem[address]]
Direct:
8d[address] ax <- ax / mem[address], bx <- ax % mem[address]
8e[address] bx <- bx / mem[address], cx <- bx % mem[address]
8f[address] cx <- cx / mem[address], dx <- cx % mem[address]
90[address] dx <- dx / mem[address], ex <- dx % mem[address]
91[address] ex <- ex / mem[address], ax <- ex % mem[address]
Immediate:
92[number] ax <- ax / number, bx <- ax % number
93[number] bx <- bx / number, cx <- bx % number
94[number] cx <- cx / number, dx <- cx % number
95[number] dx <- dx / number, ex <- dx % number
96[number] ex <- ex / number, ax <- ex % number
Register Memory Addressing:
970000 ax <- ax / mem[ax], bx <- ax % mem[ax]
970001 ax <- ax / mem[bx], bx <- ax % mem[bx]
970002 ax <- ax / mem[cx], bx <- ax % mem[cx]
970003 ax <- ax / mem[dx], bx <- ax % mem[dx]
970004 ax <- ax / mem[ex], bx <- ax % mem[ex]
970005 bx <- bx / mem[ax], cx <- bx % mem[ax]
970006 bx <- bx / mem[bx], cx <- bx % mem[bx]
970007 bx <- bx / mem[cx], cx <- bx % mem[cx]
970008 bx <- bx / mem[dx], cx <- bx % mem[dx]
970009 bx <- bx / mem[ex], cx <- bx % mem[ex]
97000a cx <- cx / mem[ax], dx <- cx % mem[ax]
97000b cx <- cx / mem[bx], dx <- cx % mem[bx]
97000c cx <- cx / mem[cx], dx <- cx % mem[cx]
97000d cx <- cx / mem[dx], dx <- cx % mem[dx]
97000e cx <- cx / mem[ex], dx <- cx % mem[ex]
97000f dx <- dx / mem[ax], ex <- dx % mem[ax]
970010 dx <- dx / mem[bx], ex <- dx % mem[bx]
970011 dx <- dx / mem[cx], ex <- dx % mem[cx]
970012 dx <- dx / mem[dx], ex <- dx % mem[dx]
970013 dx <- dx / mem[ex], ex <- dx % mem[ex]
970014 ex <- ex / mem[ax], ax <- ex % mem[ax]
970015 ex <- ex / mem[bx], ax <- ex % mem[bx]
970016 ex <- ex / mem[cx], ax <- ex % mem[cx]
970017 ex <- ex / mem[dx], ax <- ex % mem[dx]
970018 ex <- ex / mem[ex], ax <- ex % mem[ex]
Register Addressing:
980000 ax <- ax / ax, bx <- ax % ax
980001 ax <- ax / bx, bx <- ax % bx
980002 ax <- ax / cx, bx <- ax % cx
980003 ax <- ax / dx, bx <- ax % dx
980004 ax <- ax / ex, bx <- ax % ex
980005 bx <- bx / ax, cx <- bx % ax
980006 bx <- bx / bx, cx <- bx % bx
980007 bx <- bx / cx, cx <- bx % cx
980008 bx <- bx / dx, cx <- bx % dx
980009 bx <- bx / ex, cx <- bx % ex
98000a cx <- cx / ax, dx <- cx % ax
98000b cx <- cx / bx, dx <- cx % bx
98000c cx <- cx / cx, dx <- cx % cx
98000d cx <- cx / dx, dx <- cx % dx
98000e cx <- cx / ex, dx <- cx % ex
98000f dx <- dx / ax, ex <- dx % ax
980010 dx <- dx / bx, ex <- dx % bx
980011 dx <- dx / cx, ex <- dx % cx
980012 dx <- dx / dx, ex <- dx % dx
980013 dx <- dx / ex, ex <- dx % ex
980014 ex <- ex / ax, ax <- ex % ax
980015 ex <- ex / bx, ax <- ex % bx
980016 ex <- ex / cx, ax <- ex % cx
980017 ex <- ex / dx, ax <- ex % dx
980018 ex <- ex / ex, ax <- ex % ex

Indirect:
99[address] ax <> mem[mem[address]]
9a[address] bx <> mem[mem[address]]
9b[address] cx <> mem[mem[address]]
9c[address] dx <> mem[mem[address]]
9d[address] ex <> mem[mem[address]]
Direct:
9e[address] ax <> mem[address]
9f[address] bx <> mem[address]
a0[address] cx <> mem[address]
a1[address] dx <> mem[address]
a2[address] ex <> mem[address]
Immediate:
a3[number] ax <> number
a4[number] bx <> number
a5[number] cx <> number
a6[number] dx <> number
a7[number] ex <> number
Register Memory Addressing:
a80000 ax <> mem[ax]
a80001 ax <> mem[bx]
a80002 ax <> mem[cx]
a80003 ax <> mem[dx]
a80004 ax <> mem[ex]
a80005 bx <> mem[ax]
a80006 bx <> mem[bx]
a80007 bx <> mem[cx]
a80008 bx <> mem[dx]
a80009 bx <> mem[ex]
a8000a cx <> mem[ax]
a8000b cx <> mem[bx]
a8000c cx <> mem[cx]
a8000d cx <> mem[dx]
a8000e cx <> mem[ex]
a8000f dx <> mem[ax]
a80010 dx <> mem[bx]
a80011 dx <> mem[cx]
a80012 dx <> mem[dx]
a80013 dx <> mem[ex]
a80014 ex <> mem[ax]
a80015 ex <> mem[bx]
a80016 ex <> mem[cx]
a80017 ex <> mem[dx]
a80018 ex <> mem[ex]
Register Addressing:
a90000 ax <> ax
a90001 ax <> bx
a90002 ax <> cx
a90003 ax <> dx
a90004 ax <> ex
a90005 bx <> ax
a90006 bx <> bx
a90007 bx <> cx
a90008 bx <> dx
a90009 bx <> ex
a9000a cx <> ax
a9000b cx <> bx
a9000c cx <> cx
a9000d cx <> dx
a9000e cx <> ex
a9000f dx <> ax
a90010 dx <> bx
a90011 dx <> cx
a90012 dx <> dx
a90013 dx <> ex
a90014 ex <> ax
a90015 ex <> bx
a90016 ex <> cx
a90017 ex <> dx
a90018 ex <> ex

Indirect:
aa[address] ax <- mem[mem[address]]
ab[address] bx <- mem[mem[address]]
ac[address] cx <- mem[mem[address]]
ad[address] dx <- mem[mem[address]]
ae[address] ex <- mem[mem[address]]
Direct:
af[address] ax <- mem[address]
b0[address] bx <- mem[address]
b1[address] cx <- mem[address]
b2[address] dx <- mem[address]
b3[address] ex <- mem[address]
Indirect:
b4[address] mem[mem[address]] <- ax
b5[address] mem[mem[address]] <- bx
b6[address] mem[mem[address]] <- cx
b7[address] mem[mem[address]] <- dx
b8[address] mem[mem[address]] <- ex
Direct:
b9[address] mem[address] <- ax
ba[address] mem[address] <- bx
bb[address] mem[address] <- cx
bc[address] mem[address] <- dx
bd[address] mem[address] <- ex
Immediate:
be[number] ax <- number
bf[number] bx <- number
c0[number] cx <- number
c1[number] dx <- number
c2[number] ex <- number
Register addressing:
c30000 ax <- bx
c30001 ax <- cx
c30002 ax <- dx
c30003 ax <- ex
c30004 bx <- ax
c30005 bx <- cx
c30006 bx <- dx
c30007 bx <- ex
c30008 cx <- ax
c30009 cx <- bx
c3000a cx <- dx
c3000b cx <- ex
c3000c dx <- ax
c3000d dx <- bx
c3000e dx <- cx
c3000f dx <- ex
c30010 ex <- ax
c30011 ex <- bx
c30012 ex <- cx
c30013 ex <- dx

Indirect addressing:
c4[address] PC <- mem[mem[address]]
Direct addressing:
c5[address] PC <- mem[address]
Register addressing:
c60000 PC <- ax
c60001 PC <- bx
c60002 PC <- cx
c60003 PC <- dx
c60004 PC <- ex

Indirect:
c7[address] PC <- mem[mem[address]]
Direct:
c8[address] PC <- mem[address]
Register addressing:
c90000 PC <- ax
c90001 PC <- bx
c90002 PC <- cx
c90003 PC <- dx
c90004 PC <- ex

Indirect:
ca[address] PC <- mem[mem[address]]
Direct:
cb[address] PC <- mem[address]
Register addressing:
cc0000 PC <- ax
cc0001 PC <- bx
cc0002 PC <- cx
cc0003 PC <- dx
cc0004 PC <- ex

Indirect:
cd[address] PC <- mem[mem[address]]
Direct:
ce[address] PC <- mem[address]
Register addressing:
cf0000 PC <- ax
cf0001 PC <- bx
cf0002 PC <- cx
cf0003 PC <- dx
cf0004 PC <- ex

Indirect:
d0[address] PC <- mem[mem[address]]
Direct:
d1[address] PC <- mem[address]
Register addressing:
d20000 PC <- ax
d20001 PC <- bx
d20002 PC <- cx
d20003 PC <- dx
d20004 PC <- ex

Indirect:
d3[address] PC <- mem[mem[address]]
Direct:
d4[address] PC <- mem[address]
Register addressing:
d50000 PC <- ax
d50001 PC <- bx
d50002 PC <- cx
d50003 PC <- dx
d50004 PC <- ex

Register addressing:
d60000 ax <- 0
d60001 bx <- 0
d60002 cx <- 0
d60003 dx <- 0
d60004 ex <- 0

Register addressing:
d70000 ax <- ax'
d70001 bx <- bx'
d70002 cx <- cx'
d70003 dx <- dx'
d70004 ex <- ex'

Register addressing:
d80000 ax <- shl(ax)
d80001 bx <- shl(bx)
d80002 cx <- shl(cx)
d80003 dx <- shl(dx)
d80004 ex <- shl(ex)

Register addressing:
d90000 ax <- shr(ax)
d90001 bx <- shr(bx)
d90002 cx <- shr(cx)
d90003 dx <- shr(dx)
d90004 ex <- shr(ex)

Register addressing:
da0000 ax <- cil(ax)
da0001 bx <- cil(bx)
da0002 cx <- cil(cx)
da0003 dx <- cil(dx)
da0004 ex <- cil(ex)

Register addressing:
db0000 ax <- cir(ax)
db0001 bx <- cir(bx)
db0002 cx <- cir(cx)
db0003 dx <- cir(dx)
db0004 ex <- cir(ex)

Register addressing:
dc0000 ax <- ax + 1
dc0001 bx <- bx + 1
dc0002 cx <- cx + 1
dc0003 dx <- dx + 1
dc0004 ex <- ex + 1

Register addressing:
dd0000 ax <- ax - 1
dd0001 bx <- bx - 1
dd0002 cx <- cx - 1
dd0003 dx <- dx - 1
dd0004 ex <- ex - 1

de[xxxx] C <- 0

df[xxxx] C <- C'

e0[xxxx] Z <- 0

e1[xxxx] Z <- Z'

e2[xxxx] X